This invention relates to a semiconductor memory technique and further to a technique which is particularly effective for securing data stored in a non-volatile memory device. For instance, the present invention relates to a technique which will be effective when utilized for EPROM (Erasable and Programmable Read-Only Memory).
Securing data written into a non-volatile memory cell such as EPROM incorporated in a chip is necessary to prevent unauthorized acquisition of data by a third party.
A prior art method for protecting the data stored in a non-volatile memory device uses a security register which is comprised of a non-volatile memory cell distinct from a memory cell group (memory cell array) within the device. The security register inhibits access to the memory cell group from outside devices depending on the status of a specific bit or bits of this register (see "Electronic Design", published on Mar. 3, 1983, pp. 123-128).
The inventors of the present invention have observed security function failures in devices which utilize non-volatile memory for information storage by using a threshold voltage. The security transistor does not operate correctly when a power supply voltage higher than a rated value is applied thereto.
This failure will be described in further detail with reference to FIG. 7 of the accompanying drawings. FIG. 7 shows the sectional structure of a FAMOS (Floating gate Avalanche injection MOS) transistor as an example of an electrically writable non-volatile memory cell constituting EPROM. In this drawing, reference numeral 110 represents a floating gate, 111 is a control gate electrode, 112 is a source electrode and 113 is a drain electrode.
The floating gate 110 and the control gate 111 are composed of polycrystalline silicon, for example, and the source 112 and the drain 113 are an N-type region formed on a P-type silicon substrate 100. The floating gate 110, source 112 and drain 113 are separated from the substrate 100 by insulating films. The floating gate 110 and the control gate 111 are separated from each other by an insulating film, too. The floating gate 110 is completely encompassed by the insulating film.
The table below illustrates voltages applied to the electrodes in each operation mode of the memory cell. The applied voltage conditions result in either a read or write of a logic "0" or "1" to the memory cell.
TABLE 1 ______________________________________ source control gate drain substrate 112 111 113 ______________________________________ write of "0" 0 0 V.sub.pp V.sub.pp write of "1" 0 0 V.sub.cc V.sub.pp read 0 0 V.sub.cc D.sub.out ______________________________________
The "0" write operation occurs when the substrate 100 and the source 112 are grounded and a high voltage V.sub.pp (e.g. 12.5 V) is applied to the drain 113 and the control gate 111. This creates a potential gradient between the source 112 and the drain 113. This electric field accelerates some electrons to an energy level sufficient to overcome the energy barrier of the gate insulating film. These freed electrons are attracted by the potential of the control gate 111 and migrate into the floating gate 110. These electrons are encompassed by the energy barrier of the insulating film and stably exist inside the floating gate 110.
In the "1" write operation, the substrate 100 and the source 112 are grounded and the high voltage V.sub.pp and a power supply voltage V.sub.cc (e.g. 5 V) are applied to the drain 113 and to the control gate 111, respectively. Since the control gate 111 potential is low, the electron does not jump into the floating gate 110, and the gate state remains the same as before the write operation.
The state where the electron is stored in the floating gate 110 will be referred to as "0" and the state where it is not stored will be referred to as "1", though this definition is not particularly limitative. The stored information in the EPROM is erased by radiating ultraviolet rays. This radiation causes the electrons inside the floating gate 110 to acquire sufficient energy to jump from the control gate so that the memory cell enters the "1" state.
The read operation occurs when the substrate 100 and the source 112 are grounded and the power supply voltage V.sub.cc is applied to the control gate 111. The data is outputted to the drain 113 under this voltage condition.
FIG. 8 is a fundamental characteristic diagram of the memory cell. Symbol V.sub.G represents the input voltage of the control gate 111 while I.sub.SD represents the source-drain current.
In the memory cell under the "1" state, I.sub.SD starts flowing when V.sub.G is about 1 V while in the memory cell under the "0" state, I.sub.SD does not start flowing unless V.sub.G is from about 7 to about 10 V. This difference is caused by the negative voltage component resulting from the electrons stored in the floating gate 110. If the Voltage V.sub.G applied to the control gate 111 is 5 V in the read operation then the memory cell under the "1" (unwritten) state is turned ON while the memory cell under the "0" (write) state is OFF. This operation provides access to the memory information. However, if the voltage applied to control gate 111 is sufficiently high (e.g. 10 V), then the memory cell can be turned ON irrespective of its "1" or "0" state.
FIG. 9 shows an example of non-volatile memory devices used for securing data which utilize the non-volatile memory cells shown in FIG. 7. The circuit shown in FIG. 9 is one that was analyzed by the present inventors before completing the present invention.
In FIG. 9, reference numeral 51 represents a non-volatile memory cell array disposed in a matrix, 52 is an input/output (I/0) circuit, 53 is an external input/output (I/0) terminal, 54 is switch N-channel MOS transistor, 11 is a security non-volatile memory cell (transistor), 12 is a resistor and 13 is an inverter.
When security for the non-volatile memory cell array 51 is necessary, the writer operation described above occurs and the security transistor 11 transitions to the "0" (write) state. This causes the input of the inverter 13 to go to the high (H) level while the gate input of the switch transistor 54 goes to the low (L) level turning off switch (54). Accordingly, external access to the memory array is inhibited.
When the security function is not needed, the security transistor 11 is at the "1" (unwritten) state. The input of the inverter 13 is "L" while the gate input of the switch transistor 54 is "H" turning on the switch 54. This permits data access to memory cell array 51 through the external I/0 terminal 53.
If the power supply voltage is above the maximum rated value in the security system shown in FIG. 9, the security transistor 11 is turned ON, even when transistor 11 is under the write state. Thus, the data is available and no longer secure. This problem was discovered by the inventors before completion of the present invention.